Page 1 of 1

validation of source code from ACG

PostPosted: Thu May 08, 2008 6:12 pm
by jack
I am not sure whether I ought to test the source code generated by SCADE with low level requirement,or
just do this in model level? And what is the request will be in the DO-178C ?

By the way,would T-vec can translate SCADE (now SCADE support XML format)model to TVGS,like simulink tester?

Re: validation of source code from ACG

PostPosted: Fri May 09, 2008 8:22 am
by busser
jack wrote:I am not sure whether I ought to test the source code generated by SCADE with low level requirement,or
just do this in model level?


The SCADE suppliers state that the SCADE code generator produces code that is completely correct and consistent with respect to the SCADE model. However, this does not mean that the target code is correct with respect to the requirements, SCADE is a design modeling tools like Simulink and represents a chosen design/implemention rather than requirements. This also does not mean that the code will run on the target platform exactly the same way it runs in simulation. Differences in floating point processors or emulation facilities between the target platform and the SCADE simulation environment, for example, can cause completely different results for the same input values.

We would recommend using T-VEC to support verification testing at both the model and the source code level. In addition, we also recommend capturing the requirements for the SCADE models in TTM and producing requirements-based tests from these TTM modesl to run at both the model simulation and the target object code levels.

jack wrote:And what is the request will be in the DO-178C ?


DO-178C will still require requirements-based testing of the target object code on the target platform. There is an effort by the Formal Methods subgroup to include words in DO-178C and/or a supplement that will allow some verification credit for mathematical proofs that the software correctly implements a requirement, but there will be limitations on when/where such techniques may be applied and they will never completely replace all target-based software testing.

jack wrote:By the way,would T-vec can translate SCADE (now SCADE support XML format)model to TVGS,like simulink tester?


It would be possible to create a translator for SCADE models. Such a SCADE translator would be applied in the same way that the translators for Simulink and TTM models are applied. It would extract the logical paths and subsystem hierarchical structure from the SCADE model and convert it to a form that the T-VEC VGS system understands and can perform logic analysis, test vector and test driver generation processes on. However, the Simulink translator itself would not be able to translate SCADE models.