what is the different between the two generated codes?

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what is the different between the two generated codes?

Postby jack » Sat Nov 15, 2008 2:25 am

Hi,

I find that as the code generated by Simulink RTW is like;
test_Y.Out1 = (test_U.In1 && test_U.In2);

The code generated by SCADE KCG is like:
test_Y.Out1 = (test_U.In1 & test_U.In2);

Would you please tell me what is the different between them?
As logical AND have to do decision coverage analysis,but bitand don't
need decision coverage analysis.

Regards,

Jack
jack
 
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Joined: Sat Mar 15, 2008 9:59 am

Re: what is the different between the two generated codes?

Postby busser » Sat Nov 15, 2008 3:12 pm

Hi Jack

This is more of a C/C++ question and a Mathworks RTW question than a T-VEC question. But I'll be happy to answer this for you.

The logical AND expression : test_Y.Out1 = (test_U.In1 && test_U.In2);

means that if test_U.In1 can be interpreted as TRUE (if it is non-zero) AND test_U.In1 can be interpreted as TRUE (if it is non-zero) then test_Y.Out1 will be set to TRUE, it will be given a value of 1 rather than 0. Thus && has the following results

0x0f && 0xf0 = 1

The bitwise computational operator & expression : test_Y.Out1 = (test_U.In1 & test_U.In2);

means that the unsigned values of test_U.In1 and test_U.In2 are bitwise-ANDed together so the same values for test_U.In1 and test_U.In2 would produce a different result

0xaa & 0x55 = 0x00

The reason that bit-wise AND does not really enter into decision coverage is because it is not used to make decision branches in execution. It is no different than a "+" operator in this regards.
busser
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Re: what is the different between the two generated codes?

Postby jack » Sun Nov 16, 2008 7:17 am

Hi Bob,

The next question is,as the code maybe bitand or logic and,how about the coverage
analysis of the model?

Regards,

Jack
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Posts: 16
Joined: Sat Mar 15, 2008 9:59 am

Re: what is the different between the two generated codes?

Postby busser » Sun Nov 16, 2008 6:25 pm

Hi Jack

I apologize, but I am not quite sure what your question is asking about. So let me describe a simple example model with a bitwise AND block and also a logical AND block.

bitwise_and_logical_AND.png
bitwise_and_logical_AND.png (15.03 KiB) Viewed 5391 times


This code that the RTW generates for this simple model is the following.

bitwise_and_logical_AND_code.png
bitwise_and_logical_AND_code.png (7.94 KiB) Viewed 5388 times


As you can see there are no decision branches in this code. Therefore, only 1 test vector is necessary for complete MCDC code coverage. Therefore, the default set of test vectors after translation of this model with no forcePath or forceCondition options is the following

bitwise_and_logical_AND_vectors.png
bitwise_and_logical_AND_vectors.png (5.34 KiB) Viewed 5386 times


However, the code generator could implement the logical AND block using if-then-else type branching logic. Therefore, we provide translation options such as forcePaths and forceConditions. This next set of test vectors is generated from a translation using the forceConditions options. This causes DCP's for all the possible logical AND block combinations. However, because there really is only one way to implement bitwise AND, there is no additional DCP's for that block, just the default case. These are the resulting vectors.

bitwise_and_logical_AND_FC_vectors.png
bitwise_and_logical_AND_FC_vectors.png (17.03 KiB) Viewed 5390 times


Hopefully, this will answer your question. But if not, please ask again and perhaps add some additional information so that I can understand your question better.

BestRegards
Bob
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