Welcome to the T-VEC Wiki
The T-VEC wiki provides information about T-VEC's suite of tools, how to use them, and any other related information. It has no specific topic, but is for all things related to T-VEC. Everyone has access to the wiki, but only registered users can edit content. We encourage users to donate meaningful documentation and information to the T-VEC wiki.
If you are new here, you must register for a www.t-vec.com username/password. All documentation contributed is covered by the documentation license.
The Test Vector Generator System (VGS) 3.6.0 is now generally available.
T-VEC Tester for Simulink and Stateflow 4.5.0 is now generally available.
New and improved features in the Simulink Tester include:
- Improvements in the support of the following Simulink blocks - matrix concatenation, if, relay, sum, gain, product, lookup tables, data type conversion, initial condition, for,
multiport switch, subsystem, and discrete time integrator blocks.
- Stateflow chart and truth table support has been enhanced.
- Additional checks warn of model problems or issues detected during translation
- Improved Simulink simulator test driver support in default schema.
- Improved C/C++ test driver support in default schema.
- Enhanced Embedded Matlab (EML) support
- Corrected issues with default support of Matlab R14 SP2
- Sl2tvec GUI now provides explicit indications of the inline vs atomic function status of each subsystem. All Simulink subsystems that are non-atomic, or atomic-auto, or atomic-inline will be indicated as "inlined into Parent".
Please see the Release Notes for more details on the changes in this release.
The T-VEC Tabular Modeler (TTM) 4.5.0 is now generally available.
|October-2008: New coverage options name Force Block Output Propagation that extends the ForcePaths/ForceConditions coverage options.
|October-2008: Support for the translation of Embedded M-Script. []
|May-2008: New T-VEC Server Service. This may require reboot after installation. This support hyperlinking from TTM to DOORS, and VGS to Simulink Models.
|Feb-2008: Enhancements to TTM/T-VEC Model Checking features of Output and Term Table Disjointedness Checking and Mode Machine Race Condition Checking.
|Feb-2008: Updates in Simulink 2007a provide better integration for automated test driver generation of stateflow See also LDRA Integration for Model References
|May-2008: String functionality in TTM
|Adding support for Arrays in TTM - this is a significant extension to the SCR method. Please send any comments or suggestions to email@example.com.
|Table Variable are to be added to support local table variables for State and Quantification of arrays.
|Support for character indexing of strings
The multi-media video provides a quick way to get a Tool Suite Overview.
The T-VEC suite of tools provide model-based test support. The tools include:
- T-VEC Vector Generation System (VGS)
- VGS is the engine that provides model analysis, test vector generation, test driver generation, test results analysis, project status, and measurement reporting
If you're new to modeling, TTM is easy to use, and you can create your first model in a matter of minutes. TTM integrates seamlessly with VGS, and with one mouse click tests for your first model can be produced quickly. TTM has built-in help, tutorials, and course exercises built-in to the installation.
Simulink users can use SL2TVEC and VGS to support model analysis, test generation, and execution for auto-generated code, manually produced code, and the Matlab simulator.
VGS is the core T-VEC technologies developed in the late 1980's and early 1990's. It is a rather mature technology, and has not changed in any real fundamental way since the documentation. Most of the default setting provide the optimal set of tests.
Pilot Projects or Workshops are often the best way to get started with T-VEC tools.
Tvecwiki provides guidance on using the tools, from installation, tutorials, usage, and FAQs.
Other Common Questions