Difference between revisions of "Modeling"

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(Model Representation)
(Model Types)
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==Model Types==
 
==Model Types==
  
As shown in the figure, TTM provides constructs and a language to define requirement models. Simulink/Stateflow provide constructs and a language to define design models. TTM and the assertion mechanism supported by the Simulink Tester for T-VEC (SL2TVEC) provide a language and approach for defining properties (e.g., safety properties, security properties). The translators for both TTM and SL2TVEC perform modeling transformations.
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As shown in the figure, TTM provides constructs and a language to define requirement models. Simulink/Stateflow provide constructs and a language to define design models. TTM and the assertion mechanism supported by the Simulink Tester for T-VEC (SL2TVEC) provide a language and approach for defining properties (e.g., safety properties, security properties). The translators for both TTM and SL2TVEC perform modeling transformations based on translation options that result in a high-level representation called a T-VEC project that is composed of T-VEC subsystems. The subsystem language is called the T-VEC standard form. It is a textual (ASCII) language. Simplistically stated, each subsystem has one or more Functional Relationships (FRs) each associated with one or more Disjunctions (constraints). During the Build process, the T-VEC compiler converts this language into a low-level representation.
  
 
[[Image:Model_Spectrum.jpg|center|Model Spectrum]]
 
[[Image:Model_Spectrum.jpg|center|Model Spectrum]]

Revision as of 12:47, 26 February 2007