Difference between revisions of "SL2TVEC Test Driver Issues"

From T-VEC Wiki
Jump to: navigation, search
(Update Model Reference Names and Types)
Line 31: Line 31:
 
  get_rtw_types.bat --- Download it here [http://www.t-vec.com/download/get_rtw_types.bat get_rtw_types.bat]
 
  get_rtw_types.bat --- Download it here [http://www.t-vec.com/download/get_rtw_types.bat get_rtw_types.bat]
  
 +
An easy way to use the program is to put it in the c:\t-vec\bin directory. This is usually defined as one of your path variables. Then use the VGS Toolbox under Tools | Toolbox and set up as shown below:
 +
 +
[[Image:VGS_Toolbox.png|VGS Toolbox with get_rtw_types]]
 +
 +
Simply select the subsytem from the VGS Project window and then execute the get_rtw_types from the Tools menu. It will update the object mappings. Do this for each subsystem that needs to have the object mappings updated.
 +
 +
[[Image:VGS_Toolbox_Execution.png|VGS Toolbox Execution of get_rtw_types]]
 +
 +
====What the get_rtw_types program does====
 
This is a perl program that takes two parameters:
 
This is a perl program that takes two parameters:
  
Line 40: Line 49:
 
   <rtDWStruct> - defines the localDW variable relating to state data
 
   <rtDWStruct> - defines the localDW variable relating to state data
 
   <rtZCEStruct> - defines the localZCE variable relating to triggers
 
   <rtZCEStruct> - defines the localZCE variable relating to triggers
 +
 +
==

Revision as of 16:39, 24 February 2008

Contents

Simulink Tester Test Driver Issues

There are some Test Driver Generation issues related to determining object mapping information and parameter ordering, and this can limit fully automated test driver generation for RTW auto-generated code.

Function Parameter Ordering

In the release Simulink/Stateflow 2007a there is additional information now provided to support additional automated test driver generation for both Simulink and Stateflow. Support for these capabilities will be incorporated into upcoming releases.

LDRA Integration for Model References

The Simulink/Stateflow code generation process for model references is different from that of non-model reference code. The follow briefly describes how to use capabilities in T-VEC Tester for Simulink and Stateflow 4.1.0.

The typical processes include:

  • RTW Build
  • Export
  • Translate - update LDRA Schema Reference first

LDRA Schema Reference

However, there is a special schema for LDRA:

C:\T-VEC\translators\sl2tvec\test_drivers\testbed_tcf_generic.sch

Place this in the Advance Translation Options, as shown in the following image.

Advanced Translation Options

Update Model Reference Names and Types

The typical location where code is generated for a model reference is reflected by the following figure.

Model Reference Code Generation

The names extracted from the exported model information does not necessarily correspond with the different the code generation works. There is tool provided with the release called

get_rtw_types.bat --- Download it here get_rtw_types.bat

An easy way to use the program is to put it in the c:\t-vec\bin directory. This is usually defined as one of your path variables. Then use the VGS Toolbox under Tools | Toolbox and set up as shown below:

VGS Toolbox with get_rtw_types

Simply select the subsytem from the VGS Project window and then execute the get_rtw_types from the Tools menu. It will update the object mappings. Do this for each subsystem that needs to have the object mappings updated.

VGS Toolbox Execution of get_rtw_types

What the get_rtw_types program does

This is a perl program that takes two parameters:

  • Project Directory
  • Subsystem Name

It then updates the object mapping associated with that subsystem by looking through the .h file associated with the subsystem. The object mapping provides the name of the code in the user-defined variable called: <simulinkSubsystemName>. It updates two key user defined variable:

 <rtDWStruct> - defines the localDW variable relating to state data
 <rtZCEStruct> - defines the localZCE variable relating to triggers

==