SL2TVEC Test Driver Issues
There are some Test Driver Generation issues related to determining object mapping information and parameter ordering, and this can limit fully automated test driver generation for RTW auto-generated code.
Function Parameter Ordering
In the release Simulink/Stateflow 2007a there is additional information now provided to support additional automated test driver generation for both Simulink and Stateflow. Support for these capabilities will be incorporated into upcoming releases.
LDRA Integration for Model References
The Simulink/Stateflow code generation process for model references is different from that of non-model reference code. The follow briefly describes how to use capabilities in T-VEC Tester for Simulink and Stateflow 4.1.0.
The typical processes include:
- RTW Build
- Translate - update LDRA Schema Reference first
LDRA Schema Reference
However, there is a special schema for LDRA:
Place this in the Advance Translation Options, as shown in the following image.
Update Model Reference Names and Types
The typical location where code is generated for a model reference is reflected by the following figure.
The names extracted from the exported model information does not necessarily correspond with the different the code generation works. There is tool provided with the release called
get_rtw_types.bat --- Download it here get_rtw_types.bat
This is a perl program that takes two parameters:
- Project Directory
- Subsystem Name
It then updates the object mapping associated with that subsystem by looking through the .h file associated with the subsystem. The object mapping provides the name of the code in the user-defined variable called: <simulinkSubsystemName>. It updates two key user defined variable:
<rtDWStruct> - defines the localDW variable relating to state data <rtZCEStruct> - defines the localZCE variable relating to triggers