Simulink Coverage Options
Simulink diagrams often have only 1 DCPm because many Simulink blocks have implicit conditional logic. This means that the block’s implementation code can contain multiple branches of execution controlled by if-then-else constructs. In order to create a set of test vectors that will cover each of these potential statement branches, the sl2tvec translator provides a number of "forcing" options to increase test coverage.
- Translation with No Forcing or Inlining results in 1 DCP (reflecting only 1 logical path) and 2 vectors (low/high)
- Force Paths Option results in extra DCPs that are created in T-VEC Spec to ensure a test is generated for each possible output result of Simulink blocks
- Force Conditions Option results in extra DCPs that are created by translator to ensure a test is generated for each possible output result, for each input condition of Simulink blocks
Force Block Output Propagation
The new coverage options named Force Block Output Propagation (FBOP) extends the ForcePaths/ForceConditions coverage options. It is sometimes not sufficient to simply force the vector generator to select input values that cause a given block to exhibit one of its disjunctive results. The FBOP options work in conjunction with the other Forcing Options (i.e. Force Paths and Force Conditions) by extending the forcing coverage predicate definitions to include expression to constrain any “down stream” switch control pins that may need to be controlled in order that the output of the current block is allowed to flow through to affect the output of the subsystem.