Difference between revisions of "Simulink Tester Issues"

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(Model Coverage vs. Code Coverage)
(Test Sequence Vectors: State Variable Initialization)
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controlled through settings at the reference level, test sequence level or subsystem level.
 
controlled through settings at the reference level, test sequence level or subsystem level.
  
Many blocks in Simulink have specific initial condition values, unit delays, integrators, etc. (and stateflow in terms of things like initial states of state machines). T-VEC has a mechanism for using these initial values during vector generation. T=0 defines a point in time where all test vectors are generated as if the system is in the first cycle of execution. When option is T>=0 TSVs are generated for things that take place after the first cycle and then continue for multiple cycles of the TSV. When T>0 it turns off the initial condition setting action and allow the state variables to be solved for through convergence rather than be initilized/assigned.
+
Many blocks in Simulink have specific initial condition values, unit delays, integrators, etc. (and stateflow in terms of things like initial states of state machines). T-VEC has a mechanism for using these initial values during vector generation. T=0 defines a point in time where all test vectors are generated as if the system is in the first cycle of execution. When option is T>=0 TSVs are generated for things that take place after the first cycle and then continue for multiple cycles of the TSV. When T>0 it turns off the initial condition setting action and allow the state variables to be solved for through convergence rather than be initilized or assigned.
  
 
[[Image:State_Variable_Inits.jpg|center|VGS Property: State Variable Inits]]
 
[[Image:State_Variable_Inits.jpg|center|VGS Property: State Variable Inits]]

Revision as of 14:56, 25 February 2007