Difference between revisions of "Simulink Tester Issues"

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(Test Sequence Vectors)
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Test vector generation attempts to find test vectors for all of the paths (DCPs) in the model. Complete coverage means complete model coverage, however, complete model coverage does not guarantee coverage of code (e.g., MCDC coverage), for example: code generators can put in code (e.g., safety code around square root function). The Simulink Testers provides mechanisms such as assertions and coverage predicates that can be used to produce additional tests to cover many possible situations. Tools such as LDRA TBrun is integrated with the Simulink Tester and can provide test coverage measures to support organization that may need evidence to support FAA certification.
 
Test vector generation attempts to find test vectors for all of the paths (DCPs) in the model. Complete coverage means complete model coverage, however, complete model coverage does not guarantee coverage of code (e.g., MCDC coverage), for example: code generators can put in code (e.g., safety code around square root function). The Simulink Testers provides mechanisms such as assertions and coverage predicates that can be used to produce additional tests to cover many possible situations. Tools such as LDRA TBrun is integrated with the Simulink Tester and can provide test coverage measures to support organization that may need evidence to support FAA certification.
  
===Test Sequence Vectors===
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===Test Sequence Vectors: State Variable Initialization===
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Test Sequence Vectors are created by referencing the target subsystem multiple times.
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Special T-VEC subsystems are created based on a configuration file supplied to the translator.
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These TSV subsystems include one or more test sequences. Each test sequence
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includes one or more references to the target subsystem (i.e., the number of sample times
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being tested). It also includes a set of the target subsystem’s inputs for each time that the
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target subsystem is referenced. These input values have their respective subsystem reference
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appended to their name. Therefore, if a subsystem has two inputs, inputA and inputB,
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then a TSV subsystem that includes two references would include the inputs inputA_1,
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inputB_1, inputA_2 and inputB_2. Input values to each subsystem reference can be
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controlled through settings at the reference level, test sequence level or subsystem level.
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Many blocks in Simulink have specific initial condition values, unit delays, integrators, etc. (and stateflow in terms of things like initial states of state machines). T-VEC has a mechanism for using these initial values during vector generation. T=0 defines a point in time where all test vectors are generated as if the system is in the first cycle of execution. When option is T>=0 TSVs are generated for things that take place after the first cycle and then continue for multiple cycles of the TSV. When T>0 it turns off the initial condition setting action and allow the state variables to be solved for through convergence rather than be initilized/assigned.
 
Many blocks in Simulink have specific initial condition values, unit delays, integrators, etc. (and stateflow in terms of things like initial states of state machines). T-VEC has a mechanism for using these initial values during vector generation. T=0 defines a point in time where all test vectors are generated as if the system is in the first cycle of execution. When option is T>=0 TSVs are generated for things that take place after the first cycle and then continue for multiple cycles of the TSV. When T>0 it turns off the initial condition setting action and allow the state variables to be solved for through convergence rather than be initilized/assigned.
  
[Image:State_Variable_Inits.jpg|center|VGS Property: State Variable Inits]
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[[Image:State_Variable_Inits.jpg|center|VGS Property: State Variable Inits]]
  
 
The default is to generate vectors for both cases, 2 vectors per DCP when no state variables are available, but T-VEC produces 4 vectors when state variables are available.
 
The default is to generate vectors for both cases, 2 vectors per DCP when no state variables are available, but T-VEC produces 4 vectors when state variables are available.

Revision as of 14:14, 25 February 2007