Difference between revisions of "Simulink Tester Issues"

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(Inlining and Coverage)
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===Inlining and Coverage===
 
===Inlining and Coverage===
 
Use of inlining Simulink subsystems can impact test and model coverage.  
 
Use of inlining Simulink subsystems can impact test and model coverage.  
If a model includes a couple of references to division protection
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If a model includes inlined subsystems, then the missing coverage  
subsystems, which are inlined, then some, if not all, of the missing coverage  
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may be related to situations where the model doesn't support taking one of  
is related to situations where the model doesn't support taking one of  
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the paths through the utilities (lower-level subsystem) based simply on the model's design.  
the paths through these utilities (lower-level subsystem) based simply on the model's design.  
+
  
 
It is the very nature of [[Simulink Tester for T-VEC#Design Model|design models]] vs [[T-VEC_Tablular_Modeler#Requirement Modeling|requirements models]]. Designs include  
 
It is the very nature of [[Simulink Tester for T-VEC#Design Model|design models]] vs [[T-VEC_Tablular_Modeler#Requirement Modeling|requirements models]]. Designs include  
 
re-usable/generic components whose logic won't necessarily be needed for  
 
re-usable/generic components whose logic won't necessarily be needed for  
all applications. The only solution is to make sure they are treated as
+
all applications.  
stand-alone atomic functions so that they may be tested in their own right.
+
  
 
Here's an example:
 
Here's an example:
 
Subsystem X is a utility that has an input A with two paths:
 
Subsystem X is a utility that has an input A with two paths:
  
: A >= 0 -> do something
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: A >= 0 then do something
: A < 0  -> do something
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: A < 0  then do something
  
 
Subsystem Y inlines subsystem X, but has references to Subsystem X only when the input associated with the signal A is >= 0. This means that there cannot be model or test coverage for the path when A < 0.
 
Subsystem Y inlines subsystem X, but has references to Subsystem X only when the input associated with the signal A is >= 0. This means that there cannot be model or test coverage for the path when A < 0.
 +
 +
The only solution is to make sure they are treated as stand-alone atomic functions so that they may be tested in their own right.
 +
 
===Test Vector Generation Failures===
 
===Test Vector Generation Failures===
 
T-VEC VGS analysis is exhaustive in the sense that for every DCP throughout the hierarchy of systems it is model-checked, and a test vector is them produced. Most test vector generation failures results from model defects where the constraints of the DCP are not satisfiable throughout the hierarchy of DCPs of the subsystems.
 
T-VEC VGS analysis is exhaustive in the sense that for every DCP throughout the hierarchy of systems it is model-checked, and a test vector is them produced. Most test vector generation failures results from model defects where the constraints of the DCP are not satisfiable throughout the hierarchy of DCPs of the subsystems.

Revision as of 15:40, 25 February 2007