Difference between revisions of "Simulink Tester Issues"

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(Test Vector Generation Failures)
(Test Vector Generation Failures)
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===Test Vector Generation Failures===
 
===Test Vector Generation Failures===
T-VEC VGS analysis is exhaustive in the sense that for every [[Modeling#Low Level Representation|DCP]] throughout the hierarchy of systems is model-checked, and a test vector is them produced. Most test vector generation failures results from model defects where the constraints of the DCP are not satisfiable throughout the hierarchy of DCPs of the subsystems.
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T-VEC VGS analysis is exhaustive in the sense that for every [[Modeling#Low Level Representation|DCP]] throughout the hierarchy of systems is model-checked, and a test vector is then produced. Most test vector generation failures result from model defects where the constraints of the DCP are not satisfiable throughout the hierarchy of DCPs of the subsystems.
  
However, there are possible situations where test vector generation fails when it is possible to find vectors, for example when signal domains are left to their defaults. There are [[Simulink/T-VEC_Examples|default settings for ranges values]], but these may not be adequate for the application.
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However, there are possible situations where test vector generation fails when it is possible to find vectors. For example, when signal domains are left to their defaults. There are [[Simulink/T-VEC_Examples|default settings for ranges values]], but these may not be adequate for the application.
  
 
T-VEC does cover a large percentage of models that use standard blocks (see View | Library... from Simulink Tester GUI for the supported blocks), however, there are other situations where T-VEC may not produce vectors, for example
 
T-VEC does cover a large percentage of models that use standard blocks (see View | Library... from Simulink Tester GUI for the supported blocks), however, there are other situations where T-VEC may not produce vectors, for example

Revision as of 15:36, 26 February 2007