Simulink Tester Issues
This section describes potential limitations, issues and associated guidance for using T-VEC with Simulink and Stateflow.
Inlining and Coverage
Use of inlining Simulink subsystems can impact test and model coverage. If a model includes a couple of references to division protection subsystems, which are inlined, then some, if not all, of the missing coverage is related to situations where the model doesn't support taking one of the paths through these utilities (lower-level subsystem) based simply on the model's design.
It is the very nature of design models vs requirements models. Designs include re-usable/generic components whose logic won't necessarily be needed for all applications. The only solution is to make sure they are treated as stand-alone atomic functions so that they may be tested in their own right.
Here's an example: Subsystem X is a utility that has an input A with two paths:
- A >= 0 -> do something
- A < 0 -> do something
Subsystem Y inlines subsystem X, but has references to Subsystem X only when the input associated with the signal A is >= 0. This means that there cannot be model or test coverage for the path when A < 0.