Difference between revisions of "Simulink Tester for T-VEC"

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* Statement Coverage
 
* Statement Coverage
 
* Interface Coverage
 
* Interface Coverage
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See [[Simulink/T-VEC Examples|Simulink/T-VEC Examples]] for details.
  
 
==Design Model==
 
==Design Model==

Revision as of 17:34, 14 February 2007

Simulink Tester for T-VEC

The Simulink Tester for T-VEC integrates Simulink/Stateflow the the T-VEC VGS to automate much of the testing process by analyzing the Simulink model to determine the best test cases for validating the model and testing implementations of the model. When used with the Real-Time Workshop™ Generic and Embedded Coders, the T-VEC Tester generates test drivers (harnesses) for executing the test vectors against auto-generated source code. Comprehensive Test Suites

Test generation for Simulink models produces unit, integration and system level test vectors and test drivers necessary to fully verify implementations of models. The test selection process produces the set of test vectors most effective in revealing both decision and computational errors in logical, integer and floating-point domains.

VGS generates test vectors for every path through every atomic subsystem. Each test vector is determined from the constraints in the subsystem under test and the constraints of any lower-level subsystems it references. These tests produce

  • Structured Path Coverage
  • Decision (Branch) Coverage
  • Modified Condition / Decision Coverage
  • Statement Coverage
  • Interface Coverage

See Simulink/T-VEC Examples for details.

Contents

Design Model

The Mathworks' Simulink and Stateflow allow users to develop behavioral specification used as basis of for simulation or code generation, and more. When used for code generation, the models represents "what’s in the box."

Hybrid Model

Simulink was originally used for control system modeling, but with the addition of Stateflow and other features, it now provides hybrid modeling support for integrating control system and state machine models.

Model Analysis

The analysis performed prior to test vector generation identifies model errors, such as contradictions or feature interaction problems. These model errors can result in dead code or other undesirable effects.

Complete Verification Artifacts

The T-VEC Tester produces a complete set of artifacts for verifying Simulink models

  • Model Analysis Report identifies model errors
  • Test Vectors
    • Input values
    • Expected output values
    • Traceability from each test to the Simulink model
  • Test Coverage Report
  • Test Harnesses for GRT and ERT code generators
  • Test results report that details test successes and failures
  • Makefiles to fully automate the process

Scalable, Hierarchical Test Generation

Comprehensive testing is only feasible with a bottom up approach that fundamentally requires both unit and integration level testing support. When automatically generating test vectors for every condition and decision in a system, only the lowest level subsystems of the system can be tested in isolation. All higher-level subsystems must be tested in the context of the lower level subsystems on which they depend. Otherwise, there may be paths or threads in the higher-level subsystems that are not supported by the lower levels. This is especially true when multiple subsystems are related and changes could result in feature interaction problems. Some test tools generate tests based on the premise that unit testing a subsystem can ignore or stub out all subsystems on which it depends. This is a fundamentally incorrect and dangerous assumption.