Difference between revisions of "State Variable Inits"

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*Show how the test vectors are mapped through the test drivers to initialize inputs as well as state variables
 
*Show how the test vectors are mapped through the test drivers to initialize inputs as well as state variables
 
*Show how the resulting test results reflect both the inputs as well as the state variable test driver settings
 
*Show how the resulting test results reflect both the inputs as well as the state variable test driver settings
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*Demonstrate why the State Variable Inits mechanism provides the control aspects associated with multi-depth state that can be verified without the user defining Test Sequence Vector in the SL2TVEC GUI.
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The purpose of Test Sequence Vector specification is to provide the model developer with a mechanism to assess the dynamic aspects of a model or model subsystem. This is explained in the [[Test Sequence Vector Example|Test Sequence Vector Example]].
  
 
==Example Model - Single State Delay==
 
==Example Model - Single State Delay==

Revision as of 19:54, 27 February 2007