Difference between revisions of "State Variable Inits"

From T-VEC Wiki
Jump to: navigation, search
Line 1: Line 1:
This section provides a few examples to explain how the State Variable Inits test vector generation property provides a mechanism to support test coverage of Simulink constructs that have state data such as Unit Delay. The purpose of the example is to:
+
This section provides a few examples to explain how the State Variable Inits test vector generation property provides a mechanism to support test coverage of Simulink constructs that have state data such as the Unit Delay construct. The purpose of the example is to:
*Explain the vectors that are produced by the different State Variable Init settings
+
*Show example vectors that are produced by the different State Variable Init settings
 
*Show how the test vectors are mapped through the test drivers to initialize inputs as well as state variables
 
*Show how the test vectors are mapped through the test drivers to initialize inputs as well as state variables
 
*Show how the resulting test results reflect both the inputs as well as the state variable test driver settings
 
*Show how the resulting test results reflect both the inputs as well as the state variable test driver settings
*Demonstrate why the State Variable Inits mechanism provides the control aspects associated with multi-depth state that can be verified without the user defining Test Sequence Vector in the SL2TVEC GUI.
+
*Explain why the State Variable Inits mechanism provides the control aspects associated with multi-depth state that can be verified without the user defining Test Sequences in the SL2TVEC GUI.
  
The purpose of Test Sequence Vector specification is to provide the model developer with a mechanism to assess the dynamic aspects of a model or model subsystem. This is explained in the [[Test Sequence Vector Example|Test Sequence Vector Example]].
+
NOTE: The purpose of Test Sequence specification is to provide the model developer with a mechanism to assess the dynamic aspects of a model or model subsystem. This is explained in the [[Test Sequence Vector Example|Test Sequence Vector Example]].
  
 
==Example Model - Single State Delay==
 
==Example Model - Single State Delay==
The following is a simple model that contains one time delay. The inputs is a simple 8 bit integer with a range from -128 to 127.
+
The following is a simple model that contains one unit delay. The input is a simple 8 bit integer with a range from -128 to 127. The output is based on the input at time T and the unit delay from time T-1 (expect if the unit delay has an initial value at time T=0, as can be specified in Simulink).  
  
 
[[Image:Single_Time_Delay.jpg|center|Single Time Delay]]
 
[[Image:Single_Time_Delay.jpg|center|Single Time Delay]]
Line 16: Line 16:
 
The following image shows the vectors that are produced based on the different State Variable Init settings. Based on the rules, the key variable is the '''_local.IState_Unit_Delay''' variable, which is associated with the init setting:
 
The following image shows the vectors that are produced based on the different State Variable Init settings. Based on the rules, the key variable is the '''_local.IState_Unit_Delay''' variable, which is associated with the init setting:
  
* T=0 - _local.IState_Unit_Delay = 0
+
* T=0 - _local.IState_Unit_Delay = Initial Conditions from Simulink Block (See Image)
 +
[[Image:Unit_Delay_Initial_Conditions.png|right|thumb|100px|Initial Conditions]]
 
* Ignore - _local.IState_Unit_Delay  
 
* Ignore - _local.IState_Unit_Delay  
 
* T>0 - _local.IState_Unit_Delay values are based on convergence (based on low-bound or high-bound) rather than be initilized or assigned
 
* T>0 - _local.IState_Unit_Delay values are based on convergence (based on low-bound or high-bound) rather than be initilized or assigned

Revision as of 15:06, 28 February 2007