Difference between revisions of "State Variable Inits"

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(Related Topics)
 
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*Explain why the State Variable Inits mechanism provides the control aspects associated with multi-depth state that can be verified without the user defining Test Sequences in the SL2TVEC GUI.
 
*Explain why the State Variable Inits mechanism provides the control aspects associated with multi-depth state that can be verified without the user defining Test Sequences in the SL2TVEC GUI.
  
NOTE: The purpose of Test Sequence specification is to provide the model developer with a mechanism to assess the dynamic aspects of a model or model subsystem. This is explained in the [[Test Sequence Vector Example|Test Sequence Vector Example]].
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===Related Topics===
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*The purpose of Test Sequence specification is to provide the model developer with a mechanism to assess the dynamic aspects of a model or model subsystem. This is explained in the [[Test Sequence Vector Example|Test Sequence Vector Example]].
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*State Variable Inits do not impact the states in Stateflow. This is explained in [[State Flow Test Vectors|State Flow Test Vectors]].
  
 
==Example Model - Single State Delay==
 
==Example Model - Single State Delay==
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The following image shows the vectors that are produced based on the different State Variable Init settings. Based on the rules, the key variable is the '''_local.IState_Unit_Delay''' variable, which is associated with the init setting:
 
The following image shows the vectors that are produced based on the different State Variable Init settings. Based on the rules, the key variable is the '''_local.IState_Unit_Delay''' variable, which is associated with the init setting:
  
* T=0 - _local.IState_Unit_Delay = Initial Conditions from Simulink Block (See Image)
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* T=0 - _local.IState_Unit_Delay = Initial Conditions from Simulink Block (See Image below, the Initial conditions value is 0)
[[Image:Unit_Delay_Initial_Conditions.png|right|thumb|100px|Initial Conditions]]
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* Ignore - _local.IState_Unit_Delay
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[[Image:Unit_Delay_Initial_Conditions.png|center|Initial Conditions]]
* T>0 - _local.IState_Unit_Delay values are based on convergence (based on low-bound or high-bound) rather than be initilized or assigned
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* T>=0 - combines rules T=0 and T>0
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* Ignore - is treated fundamentally the same as T>0. However, it is the default setting when there are no state variables
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* T>0 - _local.IState_Unit_Delay values are solved for (i.e., through vector generation convergence), rather than initialized to their T=0 values
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* T>=0 - generates vectors for each DCP individually, first applying T=0 rule and then applying T>0 rule
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[[Image:State_Variable_Inits_and_Vectors.jpg|center|State Variable Inits and Vectors]]
 
[[Image:State_Variable_Inits_and_Vectors.jpg|center|State Variable Inits and Vectors]]
  
 
===Test Driver Mapping===
 
===Test Driver Mapping===
The RTW auto generated code makes these variable visible. Therefore, the following code illustrates how these variables are mapped to specific test driver inputs.
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The RTW auto generated code makes these variables visible. Therefore, the following code illustrates how these variables are mapped to specific test driver inputs. The two key variables include the input '''test_sequences_U.In1''' and state variable associated with the unit delay '''test_sequences_DWork.UnitDelay_DSTATE_b'''.
  
 
<table>
 
<table>
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   fprintf(ofstream, "\n");
 
   fprintf(ofstream, "\n");
 
 
</pre>
 
</pre>
 
</table>
 
</table>
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==Example Model - Double State Delay==
 
==Example Model - Double State Delay==
This rationale for being able to verify code with a single state applies to multiple state depths too, as illustrated by the following example that contains two unit delays that are sequence.
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This rationale for being able to verify code with a single state applies to multiple state depths too, as illustrated by the following example that contains two unit delays that are sequenced.
  
 
[[Image:Double_Time_Delay.png|center|Double Time Delay]]
 
[[Image:Double_Time_Delay.png|center|Double Time Delay]]
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===Test Driver Mapping===
 
===Test Driver Mapping===
The RTW auto generated code makes these variable ('''test_sequences_DWork.UnitDelay_DSTATE''' and '''test_sequences_DWork.UnitDelay1_DSTATE''') visible. Therefore, the following code illustrates how these variables are mapped to specific test driver inputs.
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The RTW auto generated code makes these two state variables ('''test_sequences_DWork.UnitDelay_DSTATE''' and '''test_sequences_DWork.UnitDelay1_DSTATE''') visible. Therefore, the following code illustrates how these variables are mapped to specific test driver inputs.
  
 
<table>
 
<table>

Latest revision as of 16:43, 28 February 2007