Difference between revisions of "State Variable Inits"

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==Example Model - Double State Delay==
 
==Example Model - Double State Delay==
This rationale for being able to verify code with a single state applies to multiple state depths too, as illustrated by the following example.
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This rationale for being able to verify code with a single state applies to multiple state depths too, as illustrated by the following example that contains two unit delays that are sequence.
 +
 
 +
[[Image:Double_Time_Delay.png|center|Double Time Delay]]
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 +
 
 +
===Vectors for State Variable Inits===
 +
 
 +
The following image shows the vectors that are produced based on the T>=0 setting force both state variables  '''_local.IState_Unit_Delay''' and '''_local.IState_Unit_Delay1''' to be converged by the vector generation, and the example further illustrates the sequenced nature of the variable values. This point is key, because the control aspects associated with multi-depth state can be verified without the user defining Test Sequence Vector control mechanisms in the SL2TVEC GUI.
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[[Image:Double_Time_Delay_vectors.png|center|Doublt Time Delay Vectors for T>=0]]
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===Test Driver Mapping===
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The RTW auto generated code makes these variable ('''test_sequences_DWork.UnitDelay_DSTATE''' and '''test_sequences_DWork.UnitDelay1_DSTATE''') visible. Therefore, the following code illustrates how these variables are mapped to specific test driver inputs.
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<table>
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<pre>
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// **** Test 1 ****
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// set outputs
 +
  test_sequences_B.Sum_e = 127;
 +
   
 +
  // set inputs
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  test_sequences_U.In2 = 127;
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  test_sequences_DWork.UnitDelay_DSTATE = 0;
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  test_sequences_DWork.UnitDelay1_DSTATE = 0;
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  // execute the test
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  test_se_DoubleTimeDelay();
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  test_s_DoubleTimeDelay_Update();
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  // print vector number and output values to results
 +
  fprintf(ofstream, "%d,", 1);
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  // __Double_Time_DelayData._output
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  fprintf(ofstream, "%d,", test_sequences_B.Sum_e);
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  printf("test %d output %d: %d,\n",1, 1, test_sequences_B.Sum_e);
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 +
  // __Double_Time_DelayData.__local.IState_Unit_Delay
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  fprintf(ofstream, "%d,", test_sequences_DWork.UnitDelay_DSTATE);
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  printf("test %d output %d: %d,\n",1, 2, test_sequences_DWork.UnitDelay_DSTATE);
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 +
  // __Double_Time_DelayData.__local.IState_Unit_Delay1
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  fprintf(ofstream, "%d,", test_sequences_DWork.UnitDelay1_DSTATE);
 +
  printf("test %d output %d: %d,\n",1, 3, test_sequences_DWork.UnitDelay1_DSTATE);
 +
 
 +
  fprintf(ofstream, "\n");
 +
</pre>
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</table>
 +
 
 +
The test driver code again is adequate for testing the control of a code subsystem, because the state variables can be set to key values that demonstrate the compliance of the auto generated code with the specification.

Revision as of 19:49, 27 February 2007

This section provides a few examples to explain how the State Variable Inits test vector generation property provides a mechanism to support test coverage of Simulink constructs that have state data such as Unit Delay. The purpose of the example is to:

  • Explain the vectors that are produced by the different State Variable Init settings
  • Show how the test vectors are mapped through the test drivers to initialize inputs as well as state variables
  • Show how the resulting test results reflect both the inputs as well as the state variable test driver settings

Contents

Example Model - Single State Delay

The following is a simple model that contains one time delay. The inputs is a simple 8 bit integer with a range from -128 to 127.

Single Time Delay

Vectors for State Variable Inits

The following image shows the vectors that are produced based on the different State Variable Init settings. Based on the rules, the key variable is the _local.IState_Unit_Delay variable, which is associated with the init setting:

  • T=0 - _local.IState_Unit_Delay = 0
  • Ignore - _local.IState_Unit_Delay
  • T>0 - _local.IState_Unit_Delay values are based on convergence (based on low-bound or high-bound) rather than be initilized or assigned
  • T>=0 - combines rules T=0 and T>0
State Variable Inits and Vectors

Test Driver Mapping

The RTW auto generated code makes these variable visible. Therefore, the following code illustrates how these variables are mapped to specific test driver inputs.

 // **** Test 1 ****
  // set outputs
  test_sequences_B.Sum = 127;
    
  // set inputs
  test_sequences_U.In1 = 127;
  test_sequences_DWork.UnitDelay_DSTATE_b = 0;
    
  // execute the test
  test_se_SingleTimeDelay();
  test_s_SingleTimeDelay_Update();
    
  // print vector number and output values to results
  fprintf(ofstream, "%d,", 1);

  // __Single_Time_DelayData._output
  fprintf(ofstream, "%d,", test_sequences_B.Sum);
  printf("test %d output %d: %d,\n",1, 1, test_sequences_B.Sum);

  // __Single_Time_DelayData.__local.IState_Unit_Delay
  fprintf(ofstream, "%d,", test_sequences_DWork.UnitDelay_DSTATE_b);
  printf("test %d output %d: %d,\n",1, 2, test_sequences_DWork.UnitDelay_DSTATE_b);

  fprintf(ofstream, "\n");

The test driver is adequate for testing the control of a code subsystem, because the state variables can be set to key values that demonstrate the compliance of the auto generated code with the specification, as reflected by the test results comparions.

Single Delay Example Test Results

Example Model - Double State Delay

This rationale for being able to verify code with a single state applies to multiple state depths too, as illustrated by the following example that contains two unit delays that are sequence.

Double Time Delay


Vectors for State Variable Inits

The following image shows the vectors that are produced based on the T>=0 setting force both state variables _local.IState_Unit_Delay and _local.IState_Unit_Delay1 to be converged by the vector generation, and the example further illustrates the sequenced nature of the variable values. This point is key, because the control aspects associated with multi-depth state can be verified without the user defining Test Sequence Vector control mechanisms in the SL2TVEC GUI.

Doublt Time Delay Vectors for T>=0

Test Driver Mapping

The RTW auto generated code makes these variable (test_sequences_DWork.UnitDelay_DSTATE and test_sequences_DWork.UnitDelay1_DSTATE) visible. Therefore, the following code illustrates how these variables are mapped to specific test driver inputs.

// **** Test 1 ****
// set outputs
  test_sequences_B.Sum_e = 127;
    
  // set inputs
  test_sequences_U.In2 = 127;
  test_sequences_DWork.UnitDelay_DSTATE = 0;
  test_sequences_DWork.UnitDelay1_DSTATE = 0;
    
  // execute the test
  test_se_DoubleTimeDelay();
  test_s_DoubleTimeDelay_Update();
    
  // print vector number and output values to results
  fprintf(ofstream, "%d,", 1);

  // __Double_Time_DelayData._output
  fprintf(ofstream, "%d,", test_sequences_B.Sum_e);
  printf("test %d output %d: %d,\n",1, 1, test_sequences_B.Sum_e);

  // __Double_Time_DelayData.__local.IState_Unit_Delay
  fprintf(ofstream, "%d,", test_sequences_DWork.UnitDelay_DSTATE);
  printf("test %d output %d: %d,\n",1, 2, test_sequences_DWork.UnitDelay_DSTATE);

  // __Double_Time_DelayData.__local.IState_Unit_Delay1
  fprintf(ofstream, "%d,", test_sequences_DWork.UnitDelay1_DSTATE);
  printf("test %d output %d: %d,\n",1, 3, test_sequences_DWork.UnitDelay1_DSTATE);

  fprintf(ofstream, "\n");

The test driver code again is adequate for testing the control of a code subsystem, because the state variables can be set to key values that demonstrate the compliance of the auto generated code with the specification.