State Variable Inits
This section provides a few examples to explain how the State Variable Inits test vector generation property provides a mechanism to support test coverage of Simulink constructs that have state data such as Unit Delay. The purpose of the example is to:
- Explain the vectors that are produced by the different State Variable Init settings
- Show how the test vectors are mapped through the test drivers to initialize inputs as well as state variables
- Show how the resulting test results reflect both the inputs as well as the state variable test driver settings
Example Model - Single State Delay
The following is a simple model that contains one time delay. The inputs is a simple 8 bit integer with a range from -128 to 127.
Vectors for State Variable Inits
The following image shows the vectors that are produced based on the different State Variable Init settings. Based on the rules, the key variable is the _local.IState_Unit_Delay variable, which is associated with the init setting:
- T=0 - _local.IState_Unit_Delay = 0
- Ignore - _local.IState_Unit_Delay
- T>0 - _local.IState_Unit_Delay values are based on convergence (based on low-bound or high-bound) rather than be initilized or assigned
- T>=0 - combines rules T=0 and T>0
Test Driver Mapping
The RTW auto generated code makes these variable visible. Therefore, the following code illustrates how these variables are mapped to specific test driver inputs.
The test driver is adequate for testing the control of a code subsystem, because the state variables can be set to key values that demonstrate the compliance of the auto generated code with the specification, as reflected by the test results comparions.
Example Model - Double State Delay
This rationale for being able to verify code with a single state applies to multiple state depths too, as illustrated by the following example.