Difference between revisions of "T-VEC Vector Generation System"

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(Code Coverage)
(Recent Changes)
 
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The T-VEC VGS has a number of advanced features and reports - see [[VGS Advanced Topics|VGS Advanced Topics]].
 
The T-VEC VGS has a number of advanced features and reports - see [[VGS Advanced Topics|VGS Advanced Topics]].
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==Recent Changes==
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<p>
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<b>The Test Vector Generator System (VGS) 3.6.0 is now generally available.</b>
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</p>
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<p>
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New and improved functionality includes:
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<ul>
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<li>New Project Explorer tab area - The Scenario View - This provides customer configuration of test vector generation on a DCP by DCP, or sets of DCPs, basis.</li>
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<li>Ability to specify ranges of DCP in Domain Convergence Paths options. ("DCP Numbers" and "Skip DCPs")</li>
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<li>Added the ability to set minimum domain boundaries for Float32 and Float64 variables</li>
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<li>Improved VGS to Simulink block navigation</li>
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<li>Improved VGS to TTM navigation</li>
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<li>1-Dimensional array support in test vector generator, in support of TTM</li>
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<li>Vector generation performance enhancements.</li>
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<li>Updated the Consult Subordinate Vectors vector generation heuristic to support TTM tables with structured outputs.</li>
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<li>Removed obsolete VGS menu items, renamed other menu items for additional clarity.</li>
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<li>Added new material to VGS Reference Guide in the section on VGS GUI.
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</li>
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</ul>
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Please see the [https://www.t-vec.com/support/secure/readme.php?ID=146 Release Notes] for more details on the changes in this release.
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</p>
  
 
==History==
 
==History==
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==Code Coverage==
 
==Code Coverage==
T-VEC tools integrate with code coverage tools such as [http://www.ldra.com/tbrun_moreinfo.asp LDRA TBrun]. The T-VEC Testers for Simulink provides users selectable options to generate test drivers in the form of LDRA TBrun .tcf files. These input/output value sets are used by TBrun when it creates test driver wrappers for the code from the input and output values, and other configuration information, that make up the .tcf files. TBrun provide measurement and reports such as MC/DC test coverage achieved by the test vectors generated by T-VEC.
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T-VEC tools integrate with code coverage tools such as [http://www.ldra.com/tbrun_moreinfo.asp LDRA TBrun] to provide a means to assess [[Model_Coverage|test code coverage]] such as MC/DC test coverage. The T-VEC Testers for Simulink provides users selectable options to generate test drivers in the form of LDRA TBrun .tcf files. These input/output value sets are used by TBrun when it creates test driver wrappers for the code from the input and output values, and other configuration information, that make up the .tcf files. TBrun provide measurement and reports such as MC/DC test coverage achieved by the test vectors generated by T-VEC.
  
 
Similar test driver configurations have been created for test drivers generated from TTM to leverage LRDA's TBrun test coverage information, and other code-based test coverage tools.
 
Similar test driver configurations have been created for test drivers generated from TTM to leverage LRDA's TBrun test coverage information, and other code-based test coverage tools.
  
The following images represents the relationship between T-VEC tools and LDRA tools. TBRun is a test execution and test results analysis tool. T-VEC can generate the TBRun .tcf scripts automatically from requirements models (TTM) and/or design models (Simulink). TBReq is a requirements traceability tool that helps organize and manage the manual creation of test scripts, based on the manual interpretation of informal requirement information, while maintaining manually created traceability links back to the informal requirements that the test vector is meant to test.
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See other [[T-VEC Tool Integrations]].
 
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The picture below shows a complete development environment that supports both model-based and also manual based aspects of software development.
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*Informal (human language) capture of requirements (DOORS)
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**Manual development of test vectors (TBRun)
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***with manual traceability back to informal requirements info (TBReq)
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**The formal modeling of requirements (TTM) and design (Simulink)
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***Automatic model analysis (TTM, Simulink Tester, T-VEC)
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****with automatic traceability back to formal and informal requirements and design info
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***Automatic code generation (Simulink)
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***Automatic generation of test vectors (T-VEC)
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****with automatic traceability back to formal and informal requirements (TTM, T-VEC) and design info (Simulink, T-VEC)
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***Automatic generation of test drivers (T-VEC)
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****with automatic traceability back to formal and informal requirements (TTM, T-VEC) and design info (Simulink, T-VEC)
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[[Image:Tool_Integration_with_LDRA.png|center|Tool Integration with LDRA]]
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See also [[VGS_Advanced_Topics#Extended MCDC Coverage|Extended MC/DC Coverage]].
  
 
==Reports, Status and Measures==
 
==Reports, Status and Measures==

Latest revision as of 07:43, 20 May 2009