SL2TVEC Version 4.5.0 (build 1936) for Windows NT 4.0, 2000, XP
May 2009

This document contains the latest information about the Simulink to T-VEC translator.

© Copyright T-VEC Technologies, Inc., 2000-2009

Windows is a trademark of Microsoft Corporation registered in the U.S. and other countries.
All other trademarks and service marks are the property of their respective owners.

The installed version of the translator can be checked by typing "sl2tvec" at the command line.

Release 4.5.0 5/09

Please Note:

Modifications were made to the model export and mappings export files used by the Simulink to T-VEC Translator. You will need to re-export any existing model export and mappings export files to use this release. The translator will write an error message to the console if an older export file is used.

Simulink-Related Updates:

·         Resolved issue where an RTW build of models with model includes failed after performing a mappings export. Previously an error indicating that the RTW target of the included model did not match that of the parent model occurred. Original models are not modified during the mappings export process but build directories are reused which caused this error. [0005686]

·         Corrected a problem forming assertion file variable names in cases where Stateflow truth table subsystems are inlined into the referencing Simulink subsystems. [0005692]

·         Combined utility subsystems that differed only by output type into one generic subsystem. [0000830]

·         Create autotypes for math operators with contant input values (Sum, Gain, and Product blocks). [0005594]

·         Copies of the sl2tvec mex files are now placed into the [T-VEC install dir]\bin\sl2tvec_dlls directory with a .dll extension. Matlab versions R14 and R14sp2 expect the mex files to have a .dll extension instead of the new standard .mexw32 extension. If you are using Matlab R14 or R14sp2 be sure to add the [T-VEC install dir]\bin\sl2tvec_dlls directory to your Matlab paths. [0005691]

·         During translation subsystems containing no outports but containing sink blocks (display, scope, stop, to workspace, to file) have those sink blocks converted to outputs and propagated as an output to the root subsystem. This is done to facilitate testing of models whose purpose is simulation. An issue in this mechanism was previously causing the translator to fail. [0005703, 0005719]

·         Mapping information for zero crossing identifiers was not being applied in map files in certain cases. Previously, map files would need to be edited to match these variables with their code names. [0005715]

·         Initialize function syntax has been corrected for Matlab versions prior to R2007b. Previously this generated a warning about too few actual parameters to the initialize function when compiling the test drivers. [0005738]

·         Stateflow block trigger ports now have <inputStruct>. prepended in the map file. Previously the missing structure information caused an unknown identifier error when building test drivers. [0005725]

·         Mappings export removes any callbacks from the duplicate model to prevent making unexpected updates as well as prevent failures due to callback processing. The original model remains unchanged. [0005534, 0005828]

·         Added support for saturation and rounding options on lookup tables with integer outputs [0005306]

·         Removed COV predicates generated for gain blocks with the option “Saturate on Integer Overflow” when the output type of the gain block is a floating point type because they are unnecessary and the results might be confusing to the user.[0005509]

·         Improved the propagation of user-defined signal types(and domains) through data type conversion blocks. Previously, the user-defined type was not propagating through such blocks. [0005588]

·         Corrected a situation where translation of a Simulink model creating a t-vec project where such a project and its artifacts already existed was overwriting any customer vector generation option settings that may have been configured in for that project. Translation now preserves those options. [0005724]

·         Initial Condition block no longer creates an un-necessary state variable. [00059771]

·         The mappings file for the root subsystem now has the correct output and update function names when separate update and output functions are used. [0005449]

·         EML functions no longer create un-necessary state variable. [0005966]

·         Merge signals feeding into an EML block are not propagated. This was causing strange naming of the EML function parameters. [0005961, 0005473]

·         Support for the abs and dot functions has been added to EML translation. [0005884]

·         EML function names in the mappings files are now correct. [0005958]

·         Simulation scripts now output results based on port name instead of port number. Previously the results file would not correspond to the expected outputs file. [0005935]

·         Correct initialization function names are included in the mappings files when a new model export is performed. [0005891, 0005934]

·         External iterator count signals are now correctly constrained to 1. Previously the un-constrained values were +/- 1.0e+012. [0005877]

·         Model with a For Iterator using an external loop count with a user defined type no longer aborts translation. [0005875]

·         Type conversion block correctly applies type to signals of width greater than one. Previously the first signal type encountered was applied to all signals feeding the type conversion block. [0005873]

·         From blocks with no associated goto now display an error when encountered during translation and the From block is interpreted as being connected to a ground block. [0005863]

·         Matrix concatenation dimensions are now correctly determined during translation. [0005843]

·         Mulitport switch utility subsystem now applies floor to the control pin value. Previously it was incorrectly applying a cast to an integer type. [0005811]

·         Corrected a situation where a floating point number, such as “1.0”, was being written as the COLUMN_NUMBER object mapping user-descriptor for vector and matrix signal objects in the .map file. This was causing a problem in the example Simulink Simulation test driver schema which was looking for a literal “1” rather than “1.0” as part of setting up the initial condition settings for the associated state variable signal(s) as part of the simulation test driver’s test setup statements.

·         Subsystems that have no output but write to data stores will have the outputFunctionCall mapping variable correctly populated. [0006012]

·         Simulink to T-VEC Translation now reports on the specific t-vec artifact files that failed during save, due to conditions like read-only attributes, etc. if such failures occur. Previously, the error message only indicated a general problem saving t-vec files and didn’t name which files were the cause of the problem.

·         Subsystem with no local output no longer creates an invalid constraint statement. [0006003]

·         Translator now creates is_conditional_init predicates for merge blocks when optional initial values are specified. [0006014]

·         Multiport switch blocks can now use the force paths setting. [0005812]

·         The translation for the truth tables has been enhanced. No longer does the input to truth tables show up in the output space. [0005748]

·         Corrected issue of incorrect variable names when with inlining subsystems. [0005802]

·         Correct initialize function is now included in the mappings export. Previously the initialize function would always be called with one parameter. [0005738,0005713]

·         MATLAB R14SP2 Discrete Time Integrator is now translated using a logical type for the previous state. Previously this type was a trigger type which has the values -1/0/1. [0006083]

·         MATLAB R14SP2 Discrete Time Integrator translation no longer creates a previous state variable when using a level reset type. [0006078]

·         Atomic subsystems that only route signals are marked as compile only in the generated VGS project. Previously test vectors and test drivers could be generated by default but there was never any matching code to execute them against. [0002699]

·         EML action names have been updated to make their locations clear. Action names now have the syntax “_loc_[line]_[column]” appended. [0005994]

·         Corrected issue in MATLAB R14SP2 and MATLAB R14SP3 translation where the Matrix Concatenation block was not being recognized as a supported block. [0006087]

·         Relay block translation with force paths no longer creates unsolvable constraint when the on/off points are equal. [0006089]

·         If and Switch blocks with unconnected or terminated actions are translated correctly and a warning that an unconnected action port is detected is displayed. Previously an unconnected action port could result in actions being associated with the wrong action port in the translated specification. [0005992, 0002508]

·         Mode width is now correctly determined for Relay Blocks. [0006138]

·         Corrected parameter order to assignment utility function when using matrix signals as an input to the assignment block. [0006145]

·         Translation of if-blocks always includes final else case. Previously the else option was not included during translation which incorrectly optimized out potential DCPs. [0006126]

Stateflow-Related Updates:

·         Resolved issue when translating a chart whose parent subsystem was not included for translation. [0005678]

·         Stateflow state enumeration values now match those of the RTW generated code. [0005735]

·         Stateflow trigger ports now have <inputStruct>. prepended in the map file. Previously an unknown identifier error due to an incomplete structure reference would prevent the default test driver from compiling. [0005725]

·         The event outputs for Stateflow charts are no longer included in the Stateflow charts output space in VGS. The function calls are inlined during translation to VGS which obsoletes the need for the function call trigger to appear in the output space. [0005832]

·         "ERROR GC0013: Function return is inconsistent with return type" is no longer displayed when only function call output exists on stateflow block. [0005882]

·         Stateflow block with only a function call output is included in translation. [0005859]

·         Function call subsystems that have duplicate names are now correctly associated to the function calls that made them during translation. Previously only one of the function call subsystems was associated to all function calls and a duplicate assertion error was printed. [0005803]

·         INFO SL0255 message no longer is being displayed for stateflow blocks. [0005798]

·         Stateflow block trigger ports now have <inputStruct>. prepended in the map file. [0005725]

·         Stateflow blocks marked as inlined are now inlined. [0005831,0005860]

·         Statemachines with no input events that are specified as atomic inlined are now inlined. [0005349]

·         Corrected issue with stateflow blocks not being able to make function calls. [0005839,0005840]

·         Data type of "Inherit: Same as Simulink" is now supported in 2008a+. [0004727,0005814]

·         Resolved issue where empty entry action in state would abort translation. [0006057]

·         Improved parsing of action types with spaces before ‘:’. Previously action types with spaces before the ‘:’ were interpreted as the last successfully processed action type which by default was an entry action type. [0006059]

sl2tvec GUI Updates:

·         Corrected a crash in sl2tvec MFC GUI when subsystem name is missing from parts of the assertion files. [0005689]

·         The preference dialog has been removed. The options provided were deprecated. [0005681]

·         Modified the sl2tvec GUI’s included subsystem display presentation to show the atomic susbsytem vs. inlined subsystem status of all included Simulink subsystems. It does this as part of the Vectors ON/OFF column of information. If a subsystem is inclined by the code generator, and thus also the Simulink to T-VEC translator, there will be no T-VEC subsystems associated with that Simulink Subsystem, so it is not possible to generate test vectors for it. This now causes the ON/OFF status to be forced to OFF. In addition, the phrase – “inlined into parent” is included as an explanation of the OFF status. [0006002]

·         The modified the sl2tvec GUI’s action on the menu item “Processing > Execute Simulation Scripts” so that it does not try to find and execute simulation test drivers for subsystems that were inlined into their parent subsystems and thus do not have any test vectors associated with them.[0006001]

Assertion File Editor:

·         Corrected a case where the assertion file editor was crashing when the subsystem name was missing from the AsrVar field in the assertion file. [0005692]

 The Example Test Driver Schemas :

·         Modified the Simulink simulation test driver schema to remove unnecessary statements in simulation test drivers that was there for setting up state variable information for signals that were not associated with state variables. These were do-nothing statements that were not necessary in these cases. [0006008]

·         Modified the Simulink simulation test driver schema so that it produces test results comparison html report files with the naming convention expected by the T-VEC VGS environment so that they are accessible via the test results report icon on the VGS tool bar and associated menu item locations. [0006005]

·         The TSV test driver schema is now creating declarations for constant values and signals at the global level. [0005998]

·         Default sl2tvec test driver schemas now support C or C++ as a target language. [0005541]

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