Release 4.6.0 9/09

Please Note:

Modifications were made to the model export and mappings export files used by the Simulink to T-VEC Translator. You will need to re-export any existing model export and mappings export files to use this release. The translator will write an error message to the console if an older export file is used.

General:

·         MFC version of the sl2tvec GUI (a windows-based GUI to replace the original Matlab GUI-builder version) is now significantly improved and is available for examination and beta usage by adding a –mfc switch to the sl2tvec GUI startup command. This version includes a new GUI Assertion Editor and a tree-structured subsystem hierarchy display, replacing the list of indented subsystem names in the original version. It also includes an tool bar with icons for common commands.

·         Corrected a problem in doing comparison between existing t-vec project system specification files (.SS files) and new version about to be written by translator process where in some cases even though there were no differences, the new .SS file was being written out anyway. This was causing the t-vec VGS subsystem to appear to need to be re-compiled and new vectors be generated causing extra VGS processing to be done. [0006241]

·         The block order export file is now removed after it has been used during model export. [0006339]

·         Start time, stop time, and execution time information is now written to the translation log. [0006342]

·         TLC options are now applied to the copy of model during mappings export. Previously the TLC options were not being applied to the copied model which could result in the mappings export failing. [0006341]

·         Matlab 2009a is now supported. [0006382]

·         If the start time for a model is not 0 then an error is displayed when attempting to perform a mappings export. Mappings export requires that an RTW build be successful which does not occur if the start time is non 0. [0006527]

·         Added a “modelDir” attribute to the top level FR definition in the .SS files being generated by the Simulink/Stateflow translator. This attribute will be used to assist T-VEC VGS navigation back to the model that the .SS file was produced from. [0006619]

·         Object mappings are now sorted alphabetically in the T-VEC VGS .map files. [0006610]

·         Warning messages are now printed to the console output and additional details are written to the translation log when significant portions of the model are optimized out during translation. [0006586, 0006562]

·         Corrected a name-clash problem when two or more inlined subsystems have local or global assertions with the same name. [0006496]

·         Added support for "Use Strong Typing with Simulink I/O" option [0006547]

·         Default domain for type “single” increased from +/-1.0E+004 to +/-1.0E+005. [0006671]

Simulink-Related Updates:

·         Improved support for using bus objects. Previously mapping information for non scalar bus objects was incorrect. [0006172, 0006164, 0006337]

·         Block priority order is now applied during translation. This corrects the issue of incorrect test vectors being generated which was sometimes seen when Memory store reads and writes were used. [0006338, 0006425, 0006401, 0006419, 0006465, 0006469, 0006470, 0006487, 0006523, 0006546, 0006596, 0006536]

·         SRF values are now correctly applied when determining iteration limits for iterator subsystems. This issue previously caused unsolvable constraints to be generated for iteration limits in some situations. [0006224]

·         First time parameter is added to the initialize function in a reusable subsystem’s mappings file when necessary. [0006389]

·         Mappings are now correct when an Inport block is virtually connected to multiple Outport blocks. [0006387]

·         outputFunction and subExternalDeclarations mapping values now have the correct values for the DWork and PWork parameters in 2008b. Previously these values needed to be hand edited. [0006048]

·         Improved algorithm for determining used signals which reduces translation time in some cases. [0006463]

·         Corrected issue where some existing RTW options were not retained in the model copy during mappings export. This issue never changed the original model and only affected the temporary model copy used during mappings export. [0006439]

·         Test driver mappings for the Unit Delay block were sometimes incorrect which would cause test driver compilation failures. [0006572, 0006573]

·         Dimension determination for Bitwise Operator block was incorrect when using the NOT operator with inputs that inherited dimensions. [0006589, 0006584]

·         Corrected issue that would incorrectly terminate an unconnected output port during translation of a block with multiple output ports. This situation occurred with the first output port was unconnected and followed by connected output ports. [0006615]

·         Pin labels are now correct in the selector utility subsystem when input is a matrix with either 1 row or 1 column. Previously the pins were labeled as if the input was a 1-D array. [0006637]

·         Added support for translation of models with Selector blocks using 0-based indexing. [0006499] [0006502]

·         Added COVerage predicate support for the 0 selector value which is viable when Selector blocks are defined to have 0-based indexing. [0006495]

·         Improved the COVerage predicates for the MIN and MAX blocks [0006511]

·         Improved the auto-determination of data types for intermediate simulink signals. [0006528]

·         The “direct look-up table nd” utility subsystems no longer are missing the runTimeData import. [0006691]

·         COV preds are now created for matrix assignment blocks with an external index port. [0006506]

·         Model location links are now included in the utility subsystems. [0005842]

·         Time Delay blocks with fixed point signals now scale the initial condition. [0006647]

EML-Related Updates:

·         Matrix assignment syntax is now supported. E.G. matrix_a(3,2)=2 [0006358]

·         Corrected issue that was causing the subExternalDeclarations mapping value to incorrectly contain the block structure when an EML function was inlined in some cases. [0006392]

·         Resolved issue with incorrect mapping names seen when a merge block connects to an inport of an EML subsystem. [0006393]

·         EML translation is now supported for Matlab R14SP2 through Matlab 2009a. Previously only Matlab 2007b, 2008a and 2009b models were supported. [0006397, 0006400]

·         Added support for the inv function. [0006456]

Stateflow-Related Updates:

·         Improved the constraints created in T-VEC VGS .SS files for representing falling edge triggers. [0005352,0006574]

·         Stateflow blocks no longer cause the block output structure to be included in the test driver when not used in the target code. [0006460]

·         Added support for inlining of graphical functions [0003274]

·         Removed the flattening of arrays into structures and are now directly supporting 1-dimensional arrays. [0006600]

·         Fixed crash that occurs while attempting to inline statecharts with parallel substates. [0006554]

·         Correct issue where some ModelLoc paths did not contain the complete path to the associated graphical function. [0006567]

·         Stateflow charts are always included in the translation even if they have no defined outputs. [0006568]

·         Zero Crossing variable is now correctly determined when written to the mapping file. [0006613]

·         Mapping name created for stateflow trigger is now correct. [0006665]

·         Mapping functions for non-inlined charts are now correct. Previously the model function names were being used when chart was not inlined. [0006666]

·         Function file name and function name mapping variables are now included for stateflow subsystems. [0006614]

·         Stateflow graphical function map files now contain the parent stateflow variables and the correct output function definition. Previously mapping variables such as blockStruct were not being included. Note that the output function is a reference to a static function generated by the RTW. In order to run test drivers the RTW code will need to be modified to remove the static option. [0006673, 0006674]

·         Stateflow subsystem mapping files now reference the stateflow chart functions instead of the model functions. [0006666]

·         The translation of a triggered stateflow block now calls the state machine subsystem with only one active event at a time. Previously the state machine subsystem was incorrectly processing the same event multiple times. [0006684]

Signal Range File-Related Updates:

·         Scientific notation is now correctly interpreted during translation when it has been applied to integer types in the SRF-editor. [0006244]

Project Makefile:

·         Better support for non-standard t-vec project folder locations [0006217]

·         Redesigned for improved performance and utility – no longer halts when any sub-make task does not complete, but continues looking for other targets to build. [0001479] [0006429]

·         Added a check to see if the RTW code is out of date with respect to the data/time of the model. If so, the make process aborts indicating that the code is out of date. [0006257]

·         Added a check to see of the current Matlab/T-VEC project is located in a Windows directory path that may be forcing the use of short-path name format in the directory path - hold-over from the DOS days. Such paths can create problems in the Make process because the Make process uses a number of Unix-like utilities, including gnu-make as the make program. If this is the case, the Make process reports this as a problem and terminates. [0006315]

·         Error message that warns about a bad MATLAB environment variable is now more explicit. It will indicate what the make file thinks is the definition of the MATLAB variable, which is actually what its definition was at the time of translation of the model. If the entire set of project files have been copied elsewhere, perhaps a different machine, and the model was not re-translated, the definition of the MATLAB variable, which is located in the <modelName>.prj.c.mak file may not reflect the current machine’s environment. This will trigger an error message about what the MATLAB environment variable was as the time of translation and suggest that the model be re-translated. [0006675]

The Example Test Driver Schemas:

·         initFunctionDefinition mapping variable value is now included as part of the external declarations section. [0006230]

·         Corrected a problem with the LDRA TBRun test driver schema that occurred if MAT file logging was turned on for the RTW generated code. [0003116]

·         Corrected a problem with the LDRA TBRun test driver schema that can occur when the Simulink RTW adds source file names in the model_sources.txt file that ultimately are not generated into the source file folder. This can happen for the file called rt_logging.c, for example. [0006346]

·         Improved the LDRA TBRun test driver schema so that the generated tcf file SearchPath variable and SH Build Command are now automatically created from list of include file paths. [0006351]

·         Improved the automatic completion of test driver map file creation by refining the SET_DESCRIPTOR fields for the enumeration literals (making them empty because you don’t want to set the value of an enumeration literal used for Stateflow test drivers and by adding a mapfile variable called <extraDefines> that provide #defines for relating the enumeration literal values in T-VEC to the integer constant values in the rtw-generated code. [0006474][0006475]

·         Changed the mapfile variable name that contains the name of the default simulink test driver schema from <schemaFile> to <defaultSchemaFile>. This is so that when the user overrides the default schema (but setting the schema file in the Advanced Translation Options dialog box) the map file variable’s value does not conflict with the actual schema file mentioned in the INCLUDE directive. [00006550]

·         Added two user-definable mapfile variables to the sl2tvec_schema.sch file. The two variables are <userTestInitialization> and <userStartupInitialization> and they allow the user to add custom startup and specific-test code sections by adding mapfile variable definitions for these variables using the sl2tvec GUI’s “Options>Mapping Variables” tool. For an example how the use of the <userTestInitialization> variable, see the Robot Model example in the T-VEC installation folder at <InstallDir>\Robot_Model\RobotModel (both levels of RobotModel in the path are significant). [0006689]

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