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T-VEC Tester for Simulink and Stateflow (sl2tvec)

Comprehensive testing of embedded systems is typically a labor-intensive and error-prone task. The T-VEC Tester for Simulink and Stateflow (sl2tvec) automates much of the testing process by analyzing the Simulink model to determine the best test cases for validating the model and testing implementations of the model. When used with the Real-Time Workshop™ Generic and Embedded Coders, the T-VEC Tester generates test drivers (harnesses) for executing the test vectors against auto-generated source code.

Comprehensive Test Suites

Test generation for Simulink models produces unit, integration and system level test vectors and test drivers necessary to fully verify implementations of models. The test selection process produces the set of test vectors most effective in revealing both decision and computational errors in logical, integer and floating-point domains.

The T-VEC Tester generates test vectors for every path through every atomic subsystem. Each test vector is determined from the constraints in the subsystem under test and the constraints of any lower-level subsystems it references. These tests produce

  • Structured Path Coverage
  • Decision (Branch) Coverage
  • Modified Condition / Decision Coverage
  • Statement Coverage
  • Interface Coverage

T-VEC Tester utilizes the most advanced test generation algorithms analyze the model's constraints (decision boundaries) and select test cases that stress every decision in the model and the extreme values of every input variable. This approach produces the tests most effective in revealing both decision and computational errors. The test vectors:

  • Stress minimum values for each path
  • Stress maximum values for each path
  • Stress minimum input values
  • Stress maximum input values

Model Analysis

The analysis performed prior to test vector generation identifies model errors, such as contradictions or feature interaction problems. These model errors can result in dead code or other undesirable effects.

Complete Verification Artifacts

The T-VEC Tester produces a complete set of artifacts for verifying Simulink models

  • Model Analysis Report identifies model errors
  • Test Vectors
    • Input values
    • Expected output values
    • Traceability from each test to the Simulink model
  • Test Coverage Report
  • Test Harnesses for GRT and ERT code generators
  • Test results report that details test successes and failures
  • Makefiles to fully automate the process

Scalable, Hierarchical Test Generation

Comprehensive testing is only feasible with a bottom up approach that fundamentally requires both unit and integration level testing support. When automatically generating test vectors for every condition and decision in a system, only the lowest level subsystems of the system can be tested in isolation. All higher-level subsystems must be tested in the context of the lower level subsystems on which they depend. Otherwise, there may be paths or threads in the higher-level subsystems that are not supported by the lower levels. This is especially true when multiple subsystems are related and changes could result in feature interaction problems. Some test tools generate tests based on the premise that unit testing a subsystem can ignore or stub out all subsystems on which it depends. This is a fundamentally incorrect and dangerous assumption.

MATLAB, Simulink, Stateflow, and Real-Time Workshop are registered trademarks of The MathWorks, Inc.

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