Technology
At the heart of our Products is the T-VEC Test Vector Generation System. It is the world's most advanced functional test generation system. It performs model analysis, test vector generation, test driver generation, test coverage analysis and test results analysis. Each T-VEC product is designed to apply the power of the Test Vector Generation System to specific software requirements or design models.
Requirements Models
Requirements describe a system's behavior or what a system is supposed to do. For software products or products that include software, these requirements are often recorded in a document using natural language. A requirements model is a more precise description of what the system is supposed to do. This precision allows tools to analyze the model and identify errors or inconsistencies. In addition, tools can generate tests from the requirement models useful for verifying that a system behaves as the original requirements prescribe.
RAVE
The RAVE solution includes methods and tools for building requirements models, performing model analysis and automating test and test driver generation. This requirements-based approach to verifying, validating, and testing software is a new paradigm for quality assurance and testing organizations to achieve unprecedented levels of productivity.
Design Models
A design describes how a system accomplishes what it is supposed to do. There are many types of design models that describe various aspects of the system's operation. When design models describe the system's behavior precisely, it is possible to analyze the model to identify errors. In addition, tools can generate tests useful for verifying that a system does what the design model describes. This approach does not ensure that the system does what it is supposed to do, but it is useful for verifying the system's behavior is consistent with the design.
T-VEC Tester for Simulink and Stateflow
Simulink is a modeling and simulation tool available from The MathWorks. It includes a graphic interface for creating software design models and the ability to generate source code from these models.
T-VEC Tester for Simulink® analyzes Simulink models for errors and generates comprehensive test suites for validating and verifying them.
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